Өргөтгөсөн мнемоник нь хэд хэдэн команд болон задардаг.
Instructions (statements) in assembly language are generally very simple, unlike those in [[high-level programming language|high-level language]]. Generally, a mnemonic is a symbolic name for a single executable machine language instruction (an [[opcode]]), and there is at least one opcode mnemonic defined for each machine language instruction. Each instruction typically consists of an ''operation'' or ''opcode'' plus zero or more ''[[operand]]s''. Most instructions refer to a single value, or a pair of values. Operands can be immediate (value coded in the instruction itself), registers specified in the instruction or implied, or the addresses of data located elsewhere in storage. This is determined by the underlying processor architecture: the assembler merely reflects how this architecture works. ''Extended mnemonics'' are often used to specify a combination of an opcode with a specific operand, e.g., the System/360 assemblers use '''B''' as an extended mnemonic for '''BC''' with a mask of 15 and '''NOP''' for '''BC''' with a mask of 0.
''Extended mnemonics'' are often used to support specialized uses of instructions, often for purposes not obvious from the instruction name. For example, many CPU's do not have an explicit NOP instruction, but do have instructions that can be used for the purpose. In 8086 CPUs the instruction ''xchg ax,ax'' is used for ''nop'', with ''nop'' being a pseudo-opcode to encode the instruction ''xchg ax,ax''. Some disassemblers recognize this and will decode the ''xchg ax,ax'' instruction as ''nop''. Similarly, IBM assemblers for [[IBM System/360|System/360]] and [[IBM System/370|System/370]] use the extended mnemonics ''NOP'' and ''NOPR'' for ''BC'' and ''BCR'' with zero masks. For the SPARC architecture, these are known as ''synthetic instructions''<ref>{{cite web |url=http://www.sparc.com/standards/V8.pdf |publisher=SPARC, International |title=The SPARC Architecture Manual, Version 8 |year=1992}}</ref>
Some assemblers also support simple built-in macro-instructions that generate two or more machine instructions. For instance, with some Z80 assemblers the instruction ''ld hl,bc'' is recognized to generate ''ld l,c'' followed by ''ld h,b''.<ref>http://www.z80.de/z80/z80code.htm</ref> These are sometimes known as ''pseudo-opcodes''.
